• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An integrated circuit having circuitry for clamping input terminals that remain unconnected after assembly into a system. A transistor is connected to clamp the input terminal to reference potential and provide regenerative feedback to a NAND circuit forming a latch which maintains the transistor on when the input terminal would otherwise be left floating. Alternatively, when the terminal is connected to supply potential, the transistor is maintained "off", precluding loss of power.
    公开号:SU1087092A3
    申请号:SU802921354
    申请日:1980-05-16
    公开日:1984-04-15
    发明作者:Кучаревски Николас
    申请人:Рка Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    2. Scheme pop.1, characterized by the fact that the control unit contains an AND-NOT element, the first and second power inputs of which are connected respectively to the first and second power inputs of the control unit, the first, second inputs and output of which are connected respectively to the first second inputs and outputs of the element is NOT
    3. Scheme pop.1, characterized in that the pulse shaping unit, when the power source is turned on, contains a resistor
    and a capacitor, the first plate of which is connected to the first power input of the pulse shaping unit when turning on the power, the output of which is connected to the second capacitor plate and to the first output of the resistor, the second lead of which is connected to the second power input of the pulse shaping unit when turning on the power
    4. Scheme pop. 1, characterized by the fact that a field-effect transistor is used as a transistor.
    5. An integrated circuit containing a common bus, an input bus, a functional logic block and a transistor having two outputs with the main type of conductivity between them and a control input. Moreover, the potential between the control input and one of the inputs
    the transistor controls its conductivity, characterized in that in order to reduce power consumption, two resistors are inserted into it, a control unit and a pulse shaping unit when the power is turned on, the output of which is connected to the control unit input, the second input of which is connected to the input bus and connected through the first resistor to the first input of the transistor, the second input of which is connected via the second resistor to the common bus, the control input of the transistor is connected to the first output of the control unit, the second output of which is connected with the input of the functional logic block
    6. The circuit according to claim 5, stating that the control unit contains two NOT elements and the NAND element, the first input of which is connected to the second input of the control unit, the first input of which is connected through the first NO element with the second input of the element IS-NOT, the output of which is connected to the first output of the control unit and to the input of the second element NOT, the output of which is connected to the second output of the control unit.
    7. The circuit according to claim 5, characterized in that a field effect transistor is used as a transistor.
    one
    The invention relates to integrated circuit technology and serves to establish the potential at the unplugged input terminals of large integrated circuits on field effect transistors.
    A known integrated circuit comprising an input bus, a common bus, a functional logic unit, a resistor and a field effect transistor, a diode.
    In the known device DP protection input functional logic block from static electricity is a diode connected between the input and the common bus 1.
    A disadvantage of the known device is that, when a power potential is supplied to the input bus, a relatively large current flows through the diode, which leads to an increase in power consumption.
    A known integrated circuit comprising two power buses, an input bus, a functional logic unit and a transistor having two inputs with a main conductivity type between them, and a control input, the potential between the control input and one of the transistor inputs controlling its conductivity, functional logic unit connected to
    the input bus and with the first input of the transistor, the second input of which is connected to the first power bus, the control input of the transistor is connected to the input bus. In the known device, the presence of a transistor at the input of a functional logic provides a relatively high input conductivity of the input of the functional logic unit and serves to eliminate the initialization of the input of the functional logic unit when exposed to random statistical charges, therefore, if there is no need to initialize the input of the functional logic unit (t. that is, in the absence of the need to implement one of the many functional possibilities of the device, the input can be left floating. the wealth of the known device is that when it is necessary to initialize the input of the functional logic block, i.e. when the input bus is connected to the second power bus, a relatively large current flows through the transistor, which can be a significant part of the current consumption of the functional logic unit, thus increasing with the power consumption. Such a condition is particularly undesirable where power is supplied from a power source with a small capacity, such as a battery for powering watches, calculators, etc. The purpose of the invention is to reduce power consumption. To achieve this goal, an integrated circuit comprising two power buses, an input bus, a functional logic unit, and a transistor having two inputs with a main conductivity type between it and a control input, and the potential between the control input and one of the inputs of the transistor controls its conductivity, the input of the functional logic unit is connected to the input bus and to the first input of the transistor, the second input of which is connected to the first power bus, the unit pack is inserted When the power is turned on, the first and second power inputs are connected to the first and second power buses, the output of the block, the power pulse is connected to the first input of the control unit, the second input and output are connected to the input bus and with the control input of the transistor. In the integrated circuit, the control unit contains an NAND element, the first and second power inputs of which are connected respectively to the first and second power inputs of the control unit, the first, second inputs and the output of which are connected respectively to the first, second inputs and output of the NAND element. In the integrated circuit, the pulse shaping unit, when the power source is turned on, contains a resistor and a capacitor, the first lining of which is connected to the first power input of the pulse shaping unit when the power is turned on, the output of which is connected to the second capacitor lining and to the first output of the resistor, the second output of which is connected to the second input powering the pulse shaping unit when the power is turned on. In an integrated circuit, a field effect transistor is used as a transistor. An integrated circuit comprising a common bus, an input bus, a functional logic unit and a transistor having two outputs with a main conductivity type between them and a control input, and the potential between the control input and one of the transistor inputs controls its conductivity, two the resistor, the control unit and the pulse shaping unit when the power is turned on, the output of which is connected to the first input of the control unit, the second input of which is connected to the input bus and connected through the first resistor to the first input transis torus, the second input of which is connected via the second resistor to the common bus, the control input of the transistor is connected to the first output of the control unit, the second output of which is connected to the input of the functional logic unit. In the integrated circuit, the control unit contains two NOT elements and the NAND element, the first input of which is connected to the second input of the control unit, the first input of which is connected via the paged element NOT to the second input of the NAND element, the output of which is connected to the first output of the JvA and with the input a second element HE, the output of which is connected to the second output of the control unit. In the integrated circuit, a field-effect transistor is used as a transistor. Figure 1 shows the scheme of the first variant of the integrated circuit; 2 is the same, the second variant of the integrated circuit. The circuit comprises an input bus 1, power supply buses 2.3, a functional logic unit 4, a control unit 5, a pulse shaping unit 6 when the power is turned on, a transistor 7, an AND element 8 , resistor 9 and capacitor 10, power inputs 5-1, 5-2 of control unit 5, inputs 6-1, 6-2 of power supply of pulse shaping unit 6 when the power is turned on. 2, the input bus 11, the common bus 12, the resistors 13, 14, the transistor 15, the pulse shaping unit 16 when the power is turned on, the control unit 17, the functional logic unit 18, the elements 19, 20 and the NOT element 21 are NOT . In Fig. 1, the input bus 1 is connected to the input of the functional logic unit 4, to the first input of the control unit 5 and to the first input of the transistor 7, the second input of which is connected to the power bus 2, to the power inputs 5-2, 6-2 of the corresponding unit 5 the control and the pulse shaping unit 6 for power supply V1, the power input 6-1 of which is connected to the power bus 3 and with the power supply input 5-1 of the control unit 5, the second input and output of which are connected respectively with the output of the pulse formation unit 6 for switching on power supply and control input isoter 7. The output, the first and the second inputs of the control unit 5 are connected respectively to the output, the first and second inputs of the element 8 AND-NOT, the first and second power inputs of which are connected respectively to the power inputs 5-2, 5-1 control unit 5. The power input 6-2 of the pulse shaping unit 6 when the power is turned on is connected through a capacitor 10 to the output of the pulse shaping unit 6 when the power is turned on, the output of which is connected through a resistor 9 to the power input 6-1 of the power generating unit 6. 2, the input bus 11 is connected to the first input of the control unit 17 and connected via a resistor 13 to the first input of the transistor 15, the second input of which is connected via a resistor to the common bus 12, the output of the pulse shaping unit 16 when the power is turned on is connected to the second input of the unit 17 control, the first and second outputs of which are connected respectively to the control input of the transistor 15 and to the input of the functional logic unit 18. The first input of the control unit 17 is connected to the first input of the AND-21 element 21, the second input of which is connected to the output the house of the element 19 is NOT, the input of which is connected to the second input of the control block 17, the first code of which is connected to the output of the element 21 NAND and the input of the element 20 of HE, the code of which is connected to the second output of the block 17 of the control. The device in FIG. 1 leads the input bus 1 to the potential of the bus 2 when nothing is supplied to the input bus 1 and prevents the loss of the shunt current through the transistor 7 when the input bus is connected with thickness 3. When the drain input of the transistor 7 is connected to the input bus 1 and the input to the source is connected to the bus 2, then the transistor 7 is selectively set to the conducting state and determined by the potential on the bus 1. The element 8 AND-NOT provides a logical output potential that is sufficient to convert the transistor 7 into conductive SOS This is any time when the potential at any input of element 8 AND-NOT has a logical low level that is close to potential n; and bus 2. Positive feedback, obtained by connecting transistor 7 and element 8 AND-NOT, holds the potential on bus 1 in the region close to the potential on bus 2, which maintains the functional logic unit 4 in the inactive state. 7 The output potential of element 8 of AND-NOT varies essentially between the potential of bus 3 and the potential of bus 2 to the corresponding logical high and low states according to stately. The application of a logical high potential to the control input (gate) of transistor 7 translates the latter into a non-linear work region in which the drain-source potential difference approaches zero, which leads to the absence of current flow between the drain and source of the transistor 7. Thus if no positive potential is applied to bus 1, then transistor 7 connects the potential of bus 1 to the potential of bus 2, which allows for greater certainty that the functional logic unit 4 will not be active It is influenced by, for example, static electricity. Block 6, which contains a resistor 9 and a capacitor 10, serves to ensure that after the occurrence of the voltage Vjju on the bus 3, the element 8 does NOT remain for some time high and potential in the state with potential. The technical element AND-NOT goes from the output state with a high level to the output state with a low level by changing the input potential by a value greater than half the supply potential, or V-Q-JJ / 2. If before the appearance of the potential VQJ, on the bus 3, the capacitor 10 is discharged, then at the occurrence of the potential Vjjj. the capacitor 10 begins to charge and approximately in time equal to 0.7 RC, where R and C are the values of the resistor and the capacitor, respectively, the potential at the corresponding input of the element 8 AND –NE reaches the value -. Therefore, after the potential Vj) j) is applied to the bus 3, the output of element 8 AND-NOT has a high logic level for a time equal to 0.7 RC. During the same time, the transistor 7 is turned on and the potential of the strip 1, if it is floating, is pulled to the integrator of the bus 2. When the potential on the bus 1 decreases to a logic low level 92 n, then the transistor 7 and the element 8 is captured by a positive feedback as previously mentioned, and pushing the potential of the tire 1 to the potential of the tire 2 occurs until a positive potential is applied to the bus 1. In another case, when the input bus 1 is supplied with the potential Vp and the power is applied to the bus 2, the element 8 AND-NO again produces at its output a high logic level impulse to force transistor 7 to conduct the impedance of the drain-source region of transistor 7 when. it is in a conductive state, is sufficiently high, which leads to the fact that the potential of the bus 1 is not pulled out of the high logic level region. After a time of 0.7 RC, the logic level at the output of element 8 becomes low and transistor 7 turns off. Transistor 7 transmits current from the power source only for a time equal to 0.7 RC, thereby reducing the power consumed by the device. This effect is increased when using element 8 AND-NOT implemented in CMOS technology. The values of the nominal values R and C must be determined taking into account the drain-source resistance of the transistor 7 in the conducting state and taking into account the parasitic capacitance of the bus 1, so that during the period of 0.7 RC it ensures the discharge of static electricity present on the parasitic capacitance bus 1, to the level of logical zero through the resistance of the drain-source region of the open transistor 7. The concrete implementation of block 6 is just an example of one of the possible ways to obtain a temporary low logic level on one of the video circuits. element 8 II-IE when turning on the power source. Other ways of generating low potential when turning on the power may be i-used, such as, for example, an invertible signal from a power-on-return circuit. The device in FIG. 2 is connected to the input bus 11 with the input of the functional logic unit 18, which prevents the charging of the input unit 18 to the power level in the absence of power, as may be the case in the device in FIG. The output level of element 20 does NOT remain low until a low level is applied at its input and the power potential is not applied. The transistor 15 and the element 21 AND-NOT form a positive feedback circuit. Resistors 13, 14 serve to reduce the current flowing through the open transistor 15 in the event that the potential of the power supply is applied to the bus. Block 16 and element 19 are NOT suis to receive, when the power is turned on, a temporary zero signal at one of the inputs of element 21 NAND, one FROM INPUT jjiciit n J o. one . The output signal of which ensured that the transistor 1 turned on. If the source potential is initially supplied to bus 11: power supply, then a high level potential does not appear at the input of unit 18 until those ghor while the output of block 16 does not show a low potential and, accordingly, the output element 19 is NOT - high potential.
    .
    k3
    /
    . It is also worth noting that instead of field-effect transistors 7.15, bipolar transistors can be used, and the transition potential at one of the inputs of the elements 8,21 AND-NOT can be provided with a single vibrator. Further, transistors 7, 15 can be connected respectively between the input lines 1, 11 and the power potential for matching the potentials of the input lines to the power potential Vjj). In this case, the elements 8.21 AND-NOT must be replaced by the elements OR-NOT, and transistors 7 and 15 should be applied to transistors of the type that are conducted during the time when the potential at their control inputs tends to potential. 2 and 12. Thus, the introduction of control units and pulse shaping units into devices when the power is turned on makes it possible to significantly reduce the power consumption current in the case of supply source potential being applied to the input buses.
    权利要求:
    Claims (1)
    [1]
    1. An integrated circuit containing two power buses, an input bus, a functional logic unit and a transistor having two inputs with the main type of conductivity between them and a control input, and the potential between the control input and one of the inputs of the transistor controls its conductivity, the input is functional the logical unit is connected to the input bus and to the first input of the transistor, the second input of which is connected to the first power bus, characterized in that, in order to reduce power consumption, a control unit and a pulse shaping when the power is turned on, the first and second power inputs of which are connected respectively to the first and second power buses, the output of the pulse forming unit when power is turned on is connected to the first input of the control unit, the second input and output of which are connected respectively to the input bus and to the control input of the transistor .
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    同族专利:
    公开号 | 公开日
    CH627912A|1982-02-15|
    US4307306A|1981-12-22|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3159751A|1960-11-25|1964-12-01|Ibm|Clamp circuit with a shunt unilateral discharge path|
    US3191067A|1962-10-23|1965-06-22|Zimmerman Herbert|Logical gating and routing circuit|
    US3303843A|1964-04-20|1967-02-14|Bunker Ramo|Amplifying circuit with controlled disabling means|
    US3636385A|1970-02-13|1972-01-18|Ncr Co|Protection circuit|
    US3878405A|1972-07-13|1975-04-15|Teradyne Inc|Switching circuitry for logical testing of network connections|
    DE2414348A1|1974-03-25|1975-10-02|Siemens Ag|Protective cct. for integrated MOS cct. - has control MOS transistor between cct. terminals and supply voltage source|
    US4094139A|1975-09-12|1978-06-13|Citizen Watch Company Limited|Display control circuit for electronic timepiece|
    GB1578657A|1976-05-25|1980-11-05|Ebauches Sa|Electronic circuit for electronic watch|JPH0332247B2|1980-04-30|1991-05-10|Nippon Electric Co|
    JPH042250B2|1982-02-03|1992-01-17|
    US4591745A|1984-01-16|1986-05-27|Itt Corporation|Power-on reset pulse generator|
    JPH01272229A|1987-07-24|1989-10-31|Nec Corp|Cmos input circuit|
    JPH0797721B2|1987-10-08|1995-10-18|原田工業株式会社|Automotive antenna controller|
    JPH01280923A|1988-05-07|1989-11-13|Mitsubishi Electric Corp|Semiconductor integrated circuit device|
    US5256919A|1990-06-05|1993-10-26|Heikka Marttila Oy|Method for preventing the oscillation of an RF power module|
    DE4234402A1|1992-10-07|1994-04-14|Siemens Ag|Arrangement for transmitting binary signals over a signal line|
    US5319259A|1992-12-22|1994-06-07|National Semiconductor Corp.|Low voltage input and output circuits with overvoltage protection|
    JP2643872B2|1994-11-29|1997-08-20|日本電気株式会社|Bonding option circuit|
    WO2008087015A2|2007-01-16|2008-07-24|Atmel Germany Gmbh|Integrated circuit|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US06/039,882|US4307306A|1979-05-17|1979-05-17|IC Clamping circuit|
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